1. REVISED SCHEDULE

04/11 - 04/17 Study different snooping protocols, discuss how we could enhance the project
04/18 - 04/24 Make test programs, use Intel Pintool to generate traces for the test programs
04/25 - 05/01 Implement LRU cache for single processor (less work owing to exams)
05/02 - 05/04 Add support for cache coherence protocols - MSI, MESI
05/05 - 05/07 Add additional protocols - MOSI, MOESI, Dragon, Firefly, etc.
05/07 - 05/09 Prepare analysis report
05/10 - 05/11 Project Presentation Preparation

2. SCHEDULE CHANGES REASON

We had earlier thought of making the basic code working before moving on to designing traces to be tested. But due to course-staff’s suggestion - “we should work on memory traces and get them ready before starting to work on the code”, we re-shuffled the order in which we approached the project.

3. WORK COMPLETED

Till now we have completed the following: 1. Studied about various snooping protocols. 2. Researched whether to use Intel’s pintool or Contech for generating memory traces. 3. Made test programs. 4. Generated memory traces for these test programs.

4. STATUS

We had to reshuffle the order in which we do things for the project. So, according to the revised order, we are running on schedule.
Yes, we should be able to meet our goals and deliverables.
Nice to haves - we are currently running on time, so should be deliverable in time.
List of goals that we’ll hit for the Parallelism competition includes, analyzing the following protocols with a “split transaction bus”:
1. MSI
2. MESI
3. MOSI
4. MOESI

5. PARALLELISM COMPETITION

We plan to show graphs that we generate after analyzing the performance of the above mentioned protocols.

6. CONCERNS

We don’t have any concerns as of now. Everything is going according to the plan.